1. Technical Field
The present invention relates to the design and modeling of large-area transistor devices.
More specifically, the invention has been developed with particular attention being paid to its possible use for modeling layout parasitic effects of large-area silicon power devices.
2. Description of the Related Art
During the last years, many efforts have been made to develop new models for power devices, which improve the degree of accuracy achieved by existing models. Recent advances in this field allowed for describing properly several physical phenomena in power devices, such as carrier velocity saturation and mobility degradation, JFET effect, non-uniform channel doping profile, non-linear charge storage effects, electro-thermal interaction, etc.
In most cases reported in literature, the device is modeled through a lumped circuit that includes compact models and a passive network that empirically takes into account the effects of layout parasitic. Alternatively, model equations for the active part of the device are properly developed from solution of the 1-D or 2-D drift-diffusion problem under simplified assumptions.
Device models generated using the lumped modeling approach are able to reproduce the DC and switching characteristics of power devices, as observed from the external terminals, with a reasonable degree of accuracy. The moderate complexity and good accuracy that characterize lumped models make them suitable for integration in circuit simulation packages for system-level performance analysis. In such cases, end-users of the model are mainly interested in optimizing the performance of the control system by choosing a proper driving circuitry for the power stage rather than improving the performance of the power device itself.
In power devices operating at moderate frequencies, the effect of layout parasites on the device switching characteristics might be safely neglected since the delay experienced by the signal traveling through the polysilicon interconnects is small compared to the rise and fall times of the input.
In this condition, all the elementary transistor cells can be turned on and off almost uniformly, which justifies the use of a lumped modeling approach.
However, the above conditions do not hold any more at higher switching frequencies, as in lighting or high-frequency DC-DC converter applications. In these cases, layout parasitic effects may limit the maximum operating frequency of the device since the time required to reach the farthest elementary transistor cells may be comparable to the switching times of the input signal.
This provides fast switching times for the cells placed close to the input pad but increasing delays for those located farther away. Moreover, the fast turn-off of only a portion of the device forces the remainder to drive a large amount of current during switching. This results in a dramatic current density increase in the slowest parts of the device that is referred to as “hot spots”.
This phenomenon is much more pronounced when the device is operated at higher switching frequencies because the current imbalance between the fastest and slowest elementary transistor cells becomes proportionally larger.
Lumped models cannot account for such phenomena, because they derive from the distributed nature of device layout parasitic effects, which are not taken into account in the model itself.